AMD is rolling out the first activation patches for its next-generation EPYC Zen 4 processors and the new features they include for the Linux operating system.
Deployment of AMD Zen 4 activation patches on Linux, RDDR5 and LRDDR5 memory support
While AMD is still not done with Zen 3 on client and server platforms, AMD’s Linux team is already rolling out the initial patches for Zen 4 support in the Linux operating system. . As reported by Phoronix, the latest fixes include support for AMD’s next-generation EPYC server chips which will offer 12-channel memory support.
AMD has already rolled out fixes that allow support for AMD EPYC processors with up to 12 CCDs, which means Linux currently has both Genoa and Bergamo added to the list. There is also new temperature monitoring support for Zen 4 processors, and the latest patch goes more on the memory front.
The new patch supports up to 12 memory channels in RDDR5 and LDDR5 versions. Both RDDR5 (Registered DDR5) and LRDDR5 (Load-Reduced DDR5) memory will be supported by AMD EPYC Zen 4 platforms with LRDDR5 for dense memory servers. Each CPU will have up to 12 memory controllers (per socket), which is an upgrade from the existing 8 controllers per chip. It is also reported that AMD’s Zen 4 chips will be marketed as’Family 7 p.m. Models 10h-1Fh and A0h-AFh‘.
The EPYC Genoa chip renderings revealed a total of 12 CCDs (16 cores per CCD) to reach 96 cores while the AMD Bergamo renderings also show 12 CCDs, but it is likely that the Zen 4C houses more cores per CCD or that the rendering displayed was not. final because a 16-core CCD configuration would mean a total of 16 Zen 4 CCDs to reach 128 cores. The final arrangement of the dies is definitely going to be an interesting sight. You can check out more information about the two next-gen AMD EPYC processor families that will launch with Zen 4 and Zen 4C cores in 2022 and 2023, respectively, here.
AMD EPYC processor families:
|Last name||AMD EPYC Naples||AMD EPYC Rome||AMD EPYC Milan||AMD EPYC Milan-X||AMD EPYC Genoa||AMD EPYC Bergamo||AMD EPYC Turin|
|Family brand image||EPYC 7001||EPYC 7002||EPYC 7003||EPYC 7003X?||EPYC 7004?||EPYC 7005?||EPYC 7006?|
|Processor architecture||Zen 1||Zen 2||Zen 3||Zen 3||Zen 4||Zen 4||Zen 5|
|Process node||Glofo 14 nm||TSMC 7 nm||TSMC 7 nm||TSMC 7 nm||5 nm TSMC||5 nm TSMC||TSMC 3nm?|
|Socket||LGA 4094||LGA 4094||LGA 4094||LGA 4094||LGA 6096||LGA 6096||LGA 6096|
|Maximum number of cores||32||64||64||64||96||128||256|
|Maximum number of threads||64||128||128||128||192||256||512|
|Maximum L3 cache||64 MB||256 MB||256 MB||768 MB?||384 MB?||To be determined||To be determined|
|Chip design||4 CCD (2 CCX per CCD)||8 CCD (2 CCX per CCD) + 1 IOD||8 CCD (1 CCX per CCD) + 1 IOD||8 CCD with 3D V-Cache (1 CCX per CCD) + 1 IOD||12 CCD (1 CCX per CCD) + 1 IOD||12 CCD (1 CCX per CCD) + 1 IOD||To be determined|
|Memory channels||8 channels||8 channels||8 channels||8 channels||12 channels||12 channels||To be determined|
|PCIe generation support||64 generation 3||128 generation 4||128 generation 4||128 generation 4||128 Gen 5||To be determined||To be determined|
|TDP range||200W||280W||280W||280W||320W (cTDP 400W)||320W (cTDP 400W)||480W (cTDP 600W)|